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ADSP-21160(HammerHead)

 

 

 Analog Devices»ç Á¦Ç°ÀÎADSP-21160(HammerHeadSHARC)À» ä¿ëÇÑ Atlas2 -3U-HS(ADSP-21160)board´Â Atlas¢â Universal Digital Signal Computer·Î ¾î¶² Çϵå¿þ¾î¸¦ »ç¿ëÇϱâ Àü¿¡ °¡»óÀ¸·Î ¾î¶² DSP½Ã½ºÅÛÀ¸·Î ±¸ÇöÇϱâÀ§ÇÑ ¸ðµç ¼ÒÇÁÆ®¿þ¾î¿Í Çϵå¿þ¾î¸¦ Æ÷ÇÔÇÑ Á¦Ç°ÀÌ´Ù. Atlas µðÀÚÀÎÀº ´Ù¸¥ DSP ¾ÆÅ°ÅØÃÄ»çÀÌÀÇ ¿Ïº®ÇÏ°Ô À̽ÄÀÌ °¡´ÉÇϱ⶧¹®¿¡ ½Ã½ºÅÛ µðÀÚÀÎÀ» ¹Ù·Î ½ÃÀÛÇÒ ¼ö ÀÖ´Ù. ÇÁ·Î¼¼¼­ ¼±Åðú º¸µå °³¹ßÀ» º´·Ä·Î ÁøÇàÇÒ ¼ö ÀÖ´Â ÀåÁ¡À» °¡Áö°í À־ Á¦Ç° °³¹ß ±â°£À» ´ÜÃàÇÒ ¼ö ÀÖ´Ù.

 

 

 

Atlas2-3U-HS board Ư¡

 

Atlas2-3U-HS board ±¸¼º

  • three HS-LINKs from each DSP are available on the rear side of the CompactPCI backplane.
  • two LINKs interconnect DSP1 and DSP2
  • one LINK per DSP is connected to the FPGA
  • all SPORTs are connected to the FPGA
  • BootROM (Flash) of DSP1 is programmable via the CompactPCI bus or DSP1
  • DSP2 is LINKBooted by DSP1
  • Timer-0 is used by Operating Systems
  • IRQ-2 (highest priority) signals an interrupt from the IP-Modules to the DSPs for data communication.
  • IRQ-1 (medium priority) signals an interrupt from the CPCI interface controller PLX9054 to the DSP1 for communication handling.
  • IRQ-0 (lowest priority) signals an interrupt from LinkPort failure detection CPLD, IP-Module or PLX9054 error output to the DSPs for Error handling.

 

  • DSP1/2(Digital Signal Processors)
    - µÎ°³ÀÇADSP-21160(HammerHead)ÇÁ·Î¼¼¼­
  • PCI controller
  • FPGA
  • Watchdog
  • Flash ROM
  • SRAM
  • IP Mezzanine Module sites
  • JTAG Interface

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